CHAPTER 019 SECTIONS · 5 CHECKS

Foundations and performance

Computer organization, memory, CPU/GPU/FPGA, Harvard and Von Neumann, clocks, Moore, and Amdahl.

Contents
  1. 1. Memory hierarchy
  2. 2. CPU, GPU, and FPGA
  3. 3. Harvard and Von Neumann
  4. 4. Clock and synchronization
  5. 5. Moore and Amdahl
  6. 6. Classic chipset layout
  7. 7. Hardware components
  8. 8. Performance metrics
  9. 9. Fundamental ideas

01

Memory hierarchy

Registers → L1 → L2/L3 → RAM → SSD/HDD: capacity and usually latency grow downward. Registers and cache sit close to compute units; storage retains data without power.

Registers~1 ns · bytesL1 cache32–128 KBL2 / L3 cacheMBsSystem memory (RAM)8–32 GB · volatileSSD / HDD0.25–2 TB · non-volatilefaster, costlierlarger, slower
The closer to the core, the faster and smaller.

02

CPU, GPU, and FPGA

A CPU excels at sequential control and general-purpose tasks. A GPU has many simpler units for massive parallelism. An FPGA is configured into a specialized datapath using an HDL.

CPUControl Unit(fetch, decode)ALU(arith, logic)RegistersL1 cachebusSystem memoryStorage (SSD)I/O devices
The CU fetches instructions, the ALU computes, registers hold operands.

03

Harvard and Von Neumann

Von Neumann shares memory/address space between instructions and data. Harvard separates them. A modern CPU may be Von Neumann at the ISA level while using split instruction/data caches internally.

Von NeumannCPUCU · ALUregistersMemoryinstructions+ dataone busHarvardCPUCU · ALUregistersInstructionmemoryDatamemoryinstructions and data share one memory→ general-purpose computersseparate memories and buses → embedded/DSP
The key difference: one shared memory or two separate ones.

04

Clock and synchronization

A clock defines state-update moments. Period T is one cycle and frequency f=1/T. A rising edge is 0→1; a falling edge is 1→0. Higher frequency alone does not guarantee higher performance.

rising edge (0→1)falling edge (1→0)period T = 1/fhigh / assertedlow / deasserted
Clock period T, levels, and edges.

05

Moore and Amdahl

Moore describes the historical growth of transistor counts. Amdahl limits speedup by the serial fraction: S(N)=1/((1−P)+P/N). For P=0.9 the limit is 10×.

05101520141664256102440961638465536P = 50%P = 75%P = 90%P = 95%number of processors N (log scale)speedup S(N)S(N) = 1 / ((1−P) + P/N)
Speedup saturates at 1/(1−P): 10× for P=90%.

06

Classic chipset layout

Northbridge linked CPU to memory and graphics; southbridge handled PCI, SATA, USB, and other I/O. Many functions now live in the CPU and PCH, but the classic layout remains an exam model.

CPUClockgeneratorNorthbridge(memory controller)front-side busMemoryslotsmemory busGraphics card(PCIe / AGP)Southbridge(I/O controller)internal busPCI slotsUSB · SATAEthernet · AudioCMOSFlash ROM (BIOS)
Northbridge: memory and graphics; southbridge: I/O.

07

Hardware components

Exams ask you to identify parts from photos: an SSD (flat 2.5″ case, non-volatile), a RAM stick (volatile system memory), a CPU cooler, a ribbon cable/bus, the CPU itself, and a USB stick. On a laptop board the GPU, CPU, and SO-DIMM RAM sit side by side; the GPU stands out with thousands of simple cores and SIMD parallelism.

SSD 2.5″Solid-state driveSystem memory (RAM)CPU coolerCommunication busCPUCPUUSB stick
The six parts from the 2024 midterm and the demo paper.
a) GPUb) CPUc) RAM
A laptop board fragment (Midterm 2025).

08

Performance metrics

Latency is the delay before execution starts; execution time runs from invocation to completion; bandwidth is the theoretical bound on concurrently executing instructions; throughput is the average actually achieved; utilization is the share of useful time. A pipeline raises throughput by overlapping the IF, ID, EX, MEM, and WB stages.

instr 1IFIDEXMEMWBinstr 2IFIDEXMEMWBinstr 3IFIDEXMEMWBinstr 4IFIDEXMEMWBt1t2t3t4t5t6t7t84 instructions in 8 cycles instead of 20 — throughput increases
A five-stage pipeline: 4 instructions in 8 cycles.

09

Fundamental ideas

The course lists: a hierarchy of memories, simplification via abstraction, Moore's law, performance via parallelism, pipelining, and speculation, dependability via redundancy, make the common case fast, and finite-state machines. For a written answer give three ideas with an example each.

SELF-CHECK

Check your understanding

Which is faster: L1 or L2?

Usually L1.

What retains data without power?

SSD, HDD, and flash/USB storage.

Amdahl limit for P=0.8?

5×.

How are f and T related?

f=1/T.

Does a pipeline improve latency or throughput?

Throughput.

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