Latches, flip-flops, and FSMs

01

S/R latch

For an active-high NOR latch: 00 hold, 01 reset, 10 set, 11 invalid. Feedback creates two stable states and stores one bit.

Build it yourself: S/R latch

02

D latch

A D latch removes the forbidden S/R combination: while enabled it is transparent and Q follows D; otherwise it holds state.

Build it yourself: D latch (enable latch)

03

Flip-flop

A flip-flop updates on a clock edge. A master–slave design uses two latches on opposite phases so the input cannot flow directly to the output.

Build it yourself: D flip-flop (rising edge) · D flip-flop (falling edge)

04

Edge and level triggering

A level-sensitive latch is active throughout an enable level. An edge-triggered flip-flop captures only at a rising or falling transition.

05

Setup, hold, metastability

D must be stable before the edge for setup time and after it for hold time. Violating this window can cause metastability.

06

Finite-state machine

An FSM has a state register and combinational next-state/output logic. At a clock edge the register accepts next state; between edges the logic computes the next transition.